Algorithm Design of Variable Symbol Rate of QAM Cable Receiver Chip

Concerning with the system level design of QAM cable receiver chip for cable HDTV DSP-based modem application, a receiver structure with joint Quadrature Amplitude Demodulator is introduced, blind decision feedback equalizer (DFE) loop, variable symbol timing recovery loop, carrier recovery loop and AGC loop. The architecture of blind DFE, with Constant Modulus Algorithm (CMA) initialization block, forward and feedback filter, operates in the passband so that equalizer can be adjusted completely independent of carrier phase. The SPWTM simulation and FPGA test confirm that proposed scheme is robust against non-impulse noise, multi-paths and carrier error.